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1 fn6876.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009. all rights reserved all other trademarks mentioned are the property of their respective owners ZL6100 adaptive digital dc/d c controller with drivers and current sharing the ZL6100 is a digital dc/dc controller with integrated mosfet drivers. current shari ng allows multiple devices to be connected in parallel to source loads with very high current demands. adaptive performance optimization algorithms improve power conversion efficiency across the entire load range. zilker labs digital-dc? technology enables a blend of power conversion performance and power management features. the ZL6100 is designed to be a flexible building block for dc power and can be easily adapted to designs ranging from a single-phase power supply operating from a 3.3v input to a multi-phase supply operating fr om a 12v input. the ZL6100 eliminates the need for complicated power supply managers as well as numerous external discrete components. all operating features can be configured by simple pin-strap/resistor selection or through the smbus? serial interface. the ZL6100 uses the pmbus? protocol for communication with a host controller and the digital-dc bus for communication between other zilker labs devices. features power conversion ? efficient synchronous buck controller ? adaptive light load efficiency optimization ? 3v to 14v input range ? 0.54v to 5.5v output range (with margin) ? 1% output voltage accuracy ? internal 3 a mosfet drivers ? fast load transient response ? current sharing and phase interleaving ? snapshot? parameter capture ? 36 ld 6mmx6mm qfn package ? pb-free (rohs compliant) power management ? digital soft-start/stop ? precision delay and ramp-up ? power-good/enable ? voltage tracking, sequencing and margining ? voltage/current/temperature monitoring ?i 2 c/smbus interface (pmbus compatible) ? output voltage and current protection ? internal non-volatile memory (nvm) applications ? servers/storage equipment ? telecom/datacom equipment ? power supplies (memory, dsp, asic, fpga) ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # ZL6100alaf* 6100 -40 to +85 36 ld qfn l36.6x6a *add ?t? or ?tk? suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. current sense ldo temp sensor v ss vtrk mgn vr vdd bst gh sw isena isenb power driver xtemp pwm gl i 2 c scl sda salrt sa management en pg cfg uvlo dly ilim fc monitor controller v25 sync vsen+ pgnd sgnd dgnd adc non- volatile memory ddc vsen- figure 1. block diagram data sheet september 8, 2009
2 fn6876.1 september 8, 2009 table of contents features ....................................................................................................................... ...................................................................... 1 power conversion ............................................................................................................... .......................................................... 1 power management.............. .............. .............. .............. .............. .............. .............. ............. ........................................................ 1 absolute maximum ratings ....................................................................................................... ........................................................ 3 thermal information............................................................................................................ ........................................................... 3 recommended operating conditions ...... .............. .............. .............. .............. ............ ........... .......... ................................................ 3 pin descriptions ............................................................................................................... ................................................................. 6 typical application circuit .................................................................................................... ............................................................. 8 ZL6100 overview ........... .............. .............. .............. .............. ........... ............ ........... .......... ............................................................... 8 digital-dc architecture ........................................................................................................ .......................................................... 8 power conversion overview ...................................................................................................... ................................................... 9 power management overview.............. .............. .............. .............. .............. ............ ........... ......... ............................................... 10 multi-mode pins ................................................................................................................ ........................................................... 10 power conversion functional descrip tion ........................................................................................ .............................................. 11 internal bias regulators and input supply connections .......................................................................... ................................... 11 high-side driver boost circuit............................. .................................................................... ..................................................... 11 output voltage selection ....................................................................................................... ...................................................... 11 start-up procedure ............................................................................................................. ......................................................... 13 soft-start delay and ramp times. ............................................................................................... ................................................ 14 power-good..................................................................................................................... ............................................................ 15 switching frequency and pll ............ .............. .............. .............. .............. ........... ........... .......... ................................................. 15 power train component selection ................................................................................................ .............................................. 16 current limit threshold selection .............................................................................................. ................................................. 19 loop compensation........... .............. .............. .............. .............. ........... ........... ........... .......... ....................................................... 22 adaptive compensation.......................................................................................................... ..................................................... 22 non-linear response (nlr) settings ............................................................................................. ............................................. 23 efficiency optimized driver dead-time control .................................................................................. ......................................... 23 adaptive diode emulation ....................................................................................................... .................................................... 23 adaptive frequency control ..................................................................................................... ................................................... 23 power management functional description................... ..................................................................... .......................................................... 24 input undervoltage lockout ......... .............. .............. .............. .............. .............. ........... .......... ..................................................... 24 output overvoltage protection ........ .............. .............. .............. .............. .............. ........... ......... .................................................. 24 output pre-bias protection ..................................................................................................... ..................................................... 24 output overcurrent protection.................................................................................................. ................................................... 25 thermal overload protection.................................................................................................... ................................................... 25 voltage tracking............................................................................................................... ........................................................... 26 voltage margining ............................................................................................................. ........................................................... 26 i 2 c/smbus communications ....................................... .................................................................. .............................................. 27 i 2 c/smbus device address selection ......................... ...................................................................... .......................................... 27 digital-dc bus ................................................................................................................. ............................................................ 28 phase spreading .............................................. .................................................................. ......................................................... 28 output sequencing .............................................................................................................. ........................................................ 28 fault spreading ................................................................................................................ ........................................................... 29 temperature monitoring using the xtemp pin.............. ....................................................................... ...................................... 29 active current sharing.... ..................................................................................................... ........................................................ 29 phase adding/dropping.......................................................................................................... ..................................................... 30 monitoring via i 2 c/smbus........................................................................................................................ .................................... 31 snapshot? parameter capture ......... ........................................................................................... .............................................. 31 non-volatile memory and device security features ...... .............. .............. .............. ........... ........... ......... .................................... 32 related tools and documentation ...... .............. .............. .............. .............. .............. ........... ......... .................................................. 32 related documentation.......................................................................................................... ......................................................... 32 revision history ............................................................................................................... ............................................................... 32 package outline drawing........................................................................................................ ........................................................ 33 ZL6100
3 fn6876.1 september 8, 2009 absolute maxi mum ratings (note 1) thermal information dc supply voltage for vdd pin. . . . . . . . . . . . . . . . . . . -0.3v to 17v logic i/o voltage for cfg, dly(0,1), en, fc(0,1), ilim(0,1), mgn, pg, sa(0,1), salrt, scl, sda, ss, sync, uvlo, v(0,1) pins . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v analog input voltages for vsen+, vsen-, vtrk, xtemp pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v analog input voltages for isena, isenb pins . . . . . . -1.5v to 6.5v mosfet drive reference for vr pin . . . . . . . . . . . . . -0.3v to 6.5v logic reference for v25 pin . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3v ground voltage differential (v dgnd -v sgnd ) for dgnd - sgnd, pgnd - sgnd pins . . . . . . . . . . . -0.3v to +0.3v high side supply voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 30v boost to switch voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 8v high side drive voltage . . . . . . . . . . . . . . (v sw - 0.3) to (v bst + 0.3) low side drive voltage . . . . . . . . . . . . . .(pgnd - 0.3) to (vr + 0.3) switch node continuous . . . . . . . . . . . . . . . . . . . (pgnd - 0.3) to 30 switch node transient (<100ns) . . . . . . . . . . . . . . (pgnd - 5) to 30 dc input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v supply thermal resistance (typical, notes 2, 3) ja (c/w) jc (c/w) 36 ld qfn . . . . . . . . . . . . . . . . . . . . . . 35 5 operating junction temperature range . . . . . . . . .-40c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions supply voltage range (typical) v dd tied to v r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0v to 5.5v v r floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v output voltage range v out (notes 1, 4) . . . . . . . . . . ..0.54 to 5.5v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. voltage measured with respect to sgnd. 2. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 3. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 4. includes margin limits. electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise specified. typical values are at t a = +25c. temperature limits established by characteri zation and are not production tested. parameter conditions min typ max unit input and supply characteristics i dd supply current at f sw = 200khz i dd supply current at f sw = 1.4mhz gh, gl no load; misc_config[7] = 1 ? ? 16 25 30 50 ma ma i dds shutdown current en = 0v no i 2 c/smbus activity ?6.5 9 ma vr reference output voltage v dd > 6v, i vr < 20ma 4.5 5.2 5.5 v v25 reference output voltage v r > 3v, i v25 < 20ma 2.25 2.5 2.75 v output characteristics output voltage adjustment range (note 5) v in > v out 0.6 ? 5.0 v output voltage set-point resolution (note 6) set using resistors ? 10 ? mv set using i 2 c/smbus ? 0.025 ? % fs (note 6) output voltage accuracy (note 7) includes line, load, temp -1 ? 1 % vsen input bias current vsen = 5.5v ? 110 200 a current sense differential input voltage (ground referenced) v isena - v isenb -100 ? 100 mv current sense differential input voltage (v out referenced; v out must be less than 4.0v) v isena - v isenb - 50 ? 50 mv current sense input bias current ground referenced -100 ? 100 a current sense input bias current (v out referenced, v out < 4.0 v) isena -1 ? 1 a isenb -100 ? 100 a soft-start delay duration range (note 8) set using dly pin or resistor 2 ? 200 ms set using i 2 c/smbus 0.002 ? 500 s ZL6100
4 fn6876.1 september 8, 2009 soft-start delay duration accuracy turn-on del ay (precise mode) (notes 8, 9) ? 0.25 ? ms turn-on delay (normal mode) (note 10) ? -1/+5 ? ms turn-off delay (note 10) ? -1/+5 ? ms soft-start ramp duration range set using ss pin or resistor 0 ? 200 ms set using i 2 c pin 0 ? 200 ms soft-start ramp duration accuracy ? 100 ? s logic input/output characteristics logic input leakage current push-pull logic pins -250 ? 250 na logic input low, v il ??0.8v logic input open (n/c) multi-mode logic pins ? 1.4 ? v logic input high, v ih 2.0 ? ? v logic output low, v ol i ol 4ma (note 15) ? ? 0.4 v logic output high, v oh i oh -2ma (note 15) 2.25 ? ? v oscillator and switching characteristics switching frequency range 200 ? 1400 khz switching frequency set-point accuracy predefined settings (see table 12) -5 ? 5 % maximum pwm duty cycle factory default 95 ? ? % minimum sync pulse width (note 14) 150 ? ? ns input clock frequency drift tolerance external clock source -13 ? 13 % gate drivers high-side driver voltage (v bst - v sw )?4.5?v high-side driver peak gate drive current (pull-down) (v bst - v sw ) = 4.5v (note 14) 2 3 ? a high-side driver pu ll-up resistance (v bst - v sw ) = 4.5v, (v bst - v gh ) = 50mv (note 14) ? 0.8 2 high-side driver pull-down resistance (v bst - v sw ) = 4.5v, (v gh - v sw ) = 50mv (note 14) ? 0.5 2 low-side driver peak gate drive current (pull-up) v r = 5v ? 2.5 ? a low-side driver peak gate drive current (pull-down) v r = 5v ? 1.8 ? a low-side driver pull-up resistance v r = 5v, (v r - v gl ) = 50mv (note 14) ? 1.2 2 low-side driver pull-down resistance v r = 5v, (v gl - pgnd) = 50mv (note 14) ? 0.5 2 switching time gh rise and fall time (v bst - v sw ) = 4.5v, c load = 2.2nf (note 14) ? 5 20 ns gl rise and fall time v r = 5v, c load = 2.2nf (note 14) ? 5 20 ns tracking vtrk input bias current vtrk = 5.5v ? 110 200 a vtrk tracking ramp accuracy 100% tracking, v out - vtrk -100 ? +100 mv vtrk regulation accuracy 100% tracking, v out - vtrk -1 ? 1 % fault protection characteristics uvlo threshold range configurable via i 2 c/smbus 2.85 ? 16 v uvlo set-point accuracy -150 ? 150 mv uvlo hysteresis factory default ? 3 ? % configurable via i 2 c/smbus 0 ? 100 % electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise specified. typical values are at t a = +25c. temperature limits established by characterization and are not production tested. (continued) parameter conditions min typ max unit ZL6100
5 fn6876.1 september 8, 2009 notes: 5. does not include margin limits. 6. percentage of full scale (fs) with temperature compensation applied. 7. v out measured at the termination of the vsen+ and vsen- sense points. 8. the device requires a delay period following an enable signal and prior to ramping its output. precise timing mode limits thi s delay period to approx 2ms, where in normal mode it may vary up to 4ms. 9. precise ramp timing mode is only valid when using en pin to enable the device rather than pmbus enable. 10. the devices may require up to a 4ms del ay following the assertion of the enable si gnal (normal mode) or following the de-ass ertion of the enable signal. 11. factory default power-good delay is set to the same value as the soft-start ramp time. 12. percentage of full scale (fs) with temperature compensation applied. 13. t sw = 1/f sw , where f sw is the switching frequency. 14. limits established by characte rization and not production tested. 15. normal capacitance of logic pins is 5pf. uvlo delay (note 14) ? ? 2.5 s power-good v out threshold factory default ? 90 ? % v out power-good v out hysteresis factory default ? 5 ? % power-good delay using pin-strap or resistor (note 11) 0 ? 200 ms configurable via i 2 c/smbus (note 14) 0 ? 500 s vsen undervoltage threshold factory default ? 85 ? % v out configurable via i 2 c/smbus (note 14) 0 ? 110 % v out vsen overvoltage threshold factory default ? 115 ? % v out configurable via i 2 c/smbus (note 14) 0 ? 115 % v out vsen undervoltage hysteresis ?5 ?% v out vsen undervoltage/overvoltage fault response time factory default ? 16 ? s configurable via i 2 c/smbus (note 14) 5 ? 60 s current limit set-point accuracy (v out referenced) ?10 ?% fs (note 12) current limit set-point accuracy (ground referenced) ?10 ?% fs (note 12) current limit protection delay factory default ? 5 ? t sw (note 13) configurable via i 2 c/smbus (note 14) 1 ? 32 t sw (note 13) temperature compensation of current limit protection threshold factory default ? 4400 ? ppm/c configurable via i 2 c/smbus (note 14) 100 ? 12700 ppm/c thermal protection threshold (junction temperature) factory default ? 125 ? c configurable via i 2 c/smbus (note 14) -40 ? 125 c thermal protection hysteresis ?15 ? c electrical specifications v dd = 12v, t a = -40c to +85c, unless otherwise specified. typical values are at t a = +25c. temperature limits established by characterization and are not production tested. (continued) parameter conditions min typ max unit ZL6100
6 fn6876.1 september 8, 2009 ZL6100 36 ld qfn top view thermal pad 27 26 25 24 23 22 21 36 35 34 33 32 10 11 12 13 14 1 2 3 4 5 6 7 dgnd sync sa0 sa1 ilim0 ilim1 scl vdd bst gh sw pgnd gl vr pg dly1 dly0 en cfg fc0 fc1 v0 v1 uvlo 8 9 20 19 15 31 16 30 isena isenb ss vtrk sda salr mgn ddc 17 18 vsen+ vsen- 29 28 xtemp v25 pin descriptions pin number label type (note 16) description 1 dgnd pwr digital ground. common return for digi tal signals. connect to low impedance ground plane. 2 sync i/o,m (note 17) clock synchronization input. used to set switching fr equency of internal clock or for synchronization to external frequency reference. 3 sa0 i, m serial address select pins. used to assign unique smbus address to each ic or to enable certain management features. 4sa1 5 ilim0 i, m current limit select. sets the overcurrent threshold voltage for isena, isenb. 6ilim1 7 scl i/o serial clock. connect to external host and/or to other zilker labs devices. 8 sda i/o serial data. connect to external host and/or to other zilker labs devices. 9 salrt o serial alert. connect to external host if desired. 10 fc0 i loop compensation selection pins. 11 fc1 12 v0 i output voltage selection pins. used to set v out set-point and v out max. 13 v1 14 uvlo i, m undervoltage lockout selection. sets the minimum value for v dd voltage to enable v out . 15 ss i, m soft start pin. set the output voltage ramp time during turn-on and turnoff. 16 vtrk i tracking sense input. used to track an external voltage source. 17 vsen+ i output voltage feedback. connect to output regulation point. 18 vsen- i output voltage feedback. connect to load return or ground regulation point. 19 isenb i differential voltage input for current limit. 20 isena i differential voltage input for current limit. high voltage tolerant. ZL6100
7 fn6876.1 september 8, 2009 21 vr pwr internal 5v reference used to power internal drivers. 22 gl o low side fet gate drive. 23 pgnd pwr power ground. connect to low impedance ground plane. 24 sw pwr drive train switch node. 25 gh o high-side fet gate drive. 26 bst pwr high-side drive boost voltage. 27 vdd (note 18) pwr supply voltage. 28 v25 pwr internal 2.5v reference used to power internal circuitry. 29 xtemp i external temperature sensor input. connec t to external 2n3904 diode connected transistor. 30 ddc i/o digital-dc bus. (open drain) commu nication between zilker labs devices. 31 mgn i signal that enables margining of output voltage. 32 cfg i, m configuration pin. used to control the switching phase offset, sequencing and other management features. 33 en i enable input. active high signal enables pwm switching. 34 dly0 i, m soft-start delay select. sets the delay from when en is asserted until the output voltage starts to ramp. 35 dly1 36 pg o power-good output. epad sgnd pwr exposed thermal pad. common return for anal og signals; internal connection to sgnd. connect to low impedance ground plane. notes: 16. i = input, o = output, pwr = power or ground. m = multi-mode pins. 17. the sync pin can be used as a logic pi n, a clock input or a clock output. 18. v dd is measured internally and the value is used to modify the pwm loop gain. pin descriptions (continued) pin number label type (note 16) description ZL6100
8 fn6876.1 september 8, 2009 typical application circuit the following application circuit represents a typical implementation of the ZL6100. for pmbus operation, it is recommended to tie the enable pin (en) to sgnd. ZL6100 overview digital-dc architecture the ZL6100 is an innovative mixed-signal power conversion and power management ic based on zilker labs patented digital-dc technology that prov ides an integrated, high performance step-down converter for a wide variety of power supply applications. today?s embedded power systems are typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal dissipation inside the system. unfortunately, ma ny of these systems are often operated at load levels far below the peak where the power system has been optimized, resulting in reduced efficiency. while this may not cause therma l stress to occur, it does contribute to higher electricity usage and results in higher overall system operating costs. zilker labs? efficiency-adaptive ZL6100 dc/dc controller helps mitigate this scenario by enabling the power converter to automatically change their operating state to increase efficiency and overall performance with little or no user interaction needed. its unique pwm loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no softwa re required, resulting in a very flexible device that is also very easy to use. an extensive set of power mana gement functions are fully integrated and can be configured using simple pin connections. the user configuration can be saved in an internal non-volatile memory (nvm). additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility. once enabled, the ZL6100 is immediately ready to regulate power and perform power management tasks with no programming required. advanced configuration options and real-time configuration changes are available via the i 2 c/smbus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub-regulation circuitry enables single supply operation from any supply between 3v and 14v with no secondary bias supplies needed. the ZL6100 can be configured by simply connecting its pins according to tables 1 and 2 provided on page 10 and page 11. additionally, a comprehensive set of online tools and application notes are available to help simplify the design process. an evaluation board is also available to help the user become familiar with the device. this board can be evaluated as a standalone platfo rm using pin configuration settings. a windows?-based gui is also provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. please refer to www.intersil. com for access to the most up-to-date documentation or call your local intersil sales office to order an evaluation kit. ZL6100 1 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 36 dgnd sync sa0 sa1 ilim0 ilim1 scl sda salrt fc0 fc1 v0 v1 uvlo ss vrtk vsen+ vdd bst gh sw pgnd gl vr isena isenb pg dly1 dly0 en cfg mgn ddc xtemp v25 v in 10f 4v c in 3 x 10f 25v l out i 2 c/smbus (note 2) power good output c v25 db bat54 cb 1f 16v qh ql 2.2h c out 2 x 47f 6.3v 4.7f c vr 6.3v v out rtn sgnd epad 12v v25 470f 2.5v pos-cap 2*220f 6.3v 100m vsen- enable f.b (note 1). ground unification 4.7f 25v ddc bus (note 3) notes: 1. ferrite bead is optional for input noise suppression 2. the i 2 c/smbus requires pull-up resistors. please refer to the i 2 c/smbus specifications for more details. 3. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the nu mber of devices connected). the 10 k [ default value, assuming a maximum of 100 pf per device, provides the necessary 1 s pull-up rise time. please refer to the ddc bus section for more details. notes: 1. ferrite bead is optional for input noise suppression 2. the i 2 c /smbus requires pull-up resistors. please refer to the i 2 c/smbus specifications for more details. 3. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the nu mber of devices connected). the 10k default value, assuming a maximum of 100pf per device, provides the necessary 1s pull-up rise time. please refer to the ddc bus section for more inform ation. figure 2. 12v to 1.8v/20a application circuit (4.5v uvlo, 10ms ss delay, 5ms ss ramp) ZL6100
9 fn6876.1 september 8, 2009 power conversion overview the ZL6100 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (pwm) control sc heme that uses external mosfets, capacitors, and an inductor to perform power conversion. figure 4 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step -down converter, as the output voltage must always be lower than the input voltage. in its most simple configuration, the ZL6100 requires two external n-channel power mosfets, one for the top control mosfet (qh) and one for the bottom synchronous mosfet (ql). the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by equation 1: during time d, qh is on and v in ? v out is applied across the inductor. the current ramps up as shown in figure 5. when qh turns off (time 1-d), the current flowing in the inductor must continue to flow from the ground up through ql, during which the current ramps down. since the output capacitor c out exhibits a low impedance at the switching frequency, the ac component of th e inductor current is filtered from the output voltage so the load sees nearly a dc voltage. typically, buck converters s pecify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. this duty cycle limit ensures that the lowside mosfet is allowed to turn on for a minimum amount of ti me during each switching cycle, which enables the bootstrap capacitor (cb in figure 4) to be charged up and provide adequat e gate drive voltage for the figure 3. ZL6100 block diagram di gi ta l compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sy nc pll power management temp sensor mux xtemp dly(0,1) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim(0,1) vd d mosfet drivers sync gen vtrk isen b vdd scl sda sa l rt > adc adc adc communication da c refcn fc( 0,1) ddc voltage sensor vsen- nvm di gi ta l compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sy nc pll power management temp sensor mux xtemp dly(0,1) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim(0,1) vd d mosfet drivers sync gen vtrk isen b vdd scl sda sa l rt > adc adc adc communication da c refcn fc( 0,1) ddc voltage sensor vsen- nvm v in v out gh gl ZL6100 sw vr bst qh ql cb db c out c in figure 4. synchronous buck converter d v out v in ------------- (eq. 1) figure 5. inductor waveform voltage (v) time current (a) v in - v out 0 -v out 1 - d i o il pk il v d ZL6100
10 fn6876.1 september 8, 2009 high-side mosfet. for more details, see ?high-side driver boost circuit? on page 11. in general, the size of components l1 and c out as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, f sw . therefore, the highest efficiency circuit may be realized by switching the mosfets at the lowest possible frequency; however, this will result in the largest component size. conversely, the smallest possible footprint may be realiz ed by switching at the fastest possible frequency but this gives a somewhat lower efficiency. each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. the block diagram for the ZL6100 is illustrated in ?typical application circuit? on page 8 in th is circuit, the target output voltage is regulated by connecting the diff erential vsen pins directly to the output regulation point. the vsen signal is then compared to a reference voltage that has been set to the desired output voltage level by the user. the error signal derived from this comparison is converted to a digital value with a low-resolution, analog-to-digital (a/d) converter. the digital signal is applied to an adjustable digital compensation filter, and the compensated signal is used to derive the appropriate pwm duty cycle for driving the external mosfets in a way that produces the desired output. the ZL6100 has several features to improve the power conversion efficiency. a non-linear response (nlr) loop improves the response time and reduces the output deviation as a result of a load transient. the ZL6100 monitors the power converter?s operating conditions and continuously adjusts the turn-on and turn-off timing of the high-side and low-side mosfets to optimize the overall efficiency of the power supply. adaptive performance optimization algorithms such as dead-time control, diode emulation, and frequency control are available to provide greater efficiency improvement. power management overview the ZL6100 incorporates a wide range of configurable power management features that are simple to implement with no external components. additionally, the ZL6100 includes circuit protection features that cont inuously safeguard the device and load from damage due to unexpected system faults. the ZL6100 can continuously moni tor input voltage, output voltage/current, internal temperature, and the temperature of an external thermal diode. a power-good output signal is also included to enable power-on reset functionality for an external processor. all power management functi ons can be configured using either pin configuration techni ques (see figure 6) or via the i 2 c/smbus interface. monitoring parameters can also be pre-configured to provide alerts for specific conditions. see application note an2033 for more details on smbus monitoring. multi-mode pins in order to simplify circuit de sign, the ZL6100 incorporates patented multi-mode pins that allow the user to easily configure many aspects of t he device with no programming. most power management featur es can be configured using these pins. the multi-mode pins can respond to four different connections as shown in table 1. these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an2033). pin-strap settings this is the simplest implementation method, as no external components are required. using this method, each pin can take on one of three possible states: low, open, or high. these pins can be connected to the v25 pin for logic high settings as this pin provides a regulated voltage higher than 2v. using a single pin, one of three settings can be selected. using two pins, one of nine settings can be selected. multi-mode pin configuration resistor settings this method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. i 2 c/smbus method almost any ZL6100 function can be configured via the i 2 c/smbus interface using standard pmbus commands. additionally, any value that has been configured using the pin-strap or resistor setting methods can also be re-configured and/or verified via the i 2 c/smbus. see application note an2033 for more details. table 1. multi-mode pin configuration pin tied to value low (logic low) < 0.8vdc open (n/c) no connection high (logic high) > 2.0vdc resistor to sgnd set by resistor value figure 6. pin-strap and resistor setting examples ZL6100 multi-mode pin ZL6100 r set logic high logic low open pin-strap settings resistor settings multi-mode pin ZL6100
11 fn6876.1 september 8, 2009 the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa0 and sa1 pins. vout_max is determined as 10% greater than the voltage set by the v0 and v1 pins. power conversion functional description internal bias regulators and input supply connections the ZL6100 employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the internal bias regulators are as follows: ? vr:the vr ldo provides a regulated 5v bias supply for the mosfet driver circuits. it is powered from the vdd pin. a 4.7f filter capacitor is required at the vr pin. ? v25:the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. a 10f filter capacitor is required at the v25 pin. when the input supply (vdd) is higher than 5.5v, the vr pin should not be connected to any other pins. it should only have a filter capacitor attached as shown in figure 7. due to the dropout voltage associated with the vr bias regulator, the vdd pin must be connected to the vr pin for designs operating from a supply below 5.5v. figure 7 illustrates the required connections for both cases. note: the internal bias regulators are not designed to be outputs for powering other circuitry. do not attach external loads to any of these pins. the multi-mode pins may be connected to the v25 pin for logic high settings. high-side driver boost circuit the gate drive voltage for the high-side mosfet driver is generated by a floating bootstrap capacitor, cb (see figure 4). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through diode db. when ql turns off and the upper mosfet (qh) turns on, the sw node is pulled up to v dd and the voltage on the bootstrap capacitor is boosted approximately 5v above v dd to provide the necessary voltage to power the high-side driver. a schottky diode should be used for db to help maximize the high-side drive supply voltage. output voltage selection standard mode the output voltage may be set to any voltage between 0.6v and 5.0v provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maxi mum duty cycle specification. using the pin-strap method, v out can be set to any of nine standard voltages as shown in table 2. the resistor setting method can be used to set the output voltage to levels not available in table 2. resistors r0 and r1 are selected to produce a specific voltage between 0.6v and 5.0v in 10mv steps. resistor r1 provides a coarse setting and resistor r0 prov ides a fine adjustment, thus eliminating the additional errors associated with using two 1% resistors (this typically adds ~1.4% error). to set v out using resistors, follow the steps below to calculate an index value and then use table 3 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1: index1 = 4 x v out (v out in 10mv steps) 2. round the result down to the nearest whole number. 3. select the value of r1 from table 3 using the index1 rounded value from step 2. 4. calculate index0: index0 = 100 x v out ? (25 x index1) 5. select the value of r0 from table 3 using the index0 value from step 4. figure 7. input supply connections v in vdd vr ZL6100 v in vdd vr ZL6100 3v v in 5.5v 5.5v < v in 14v table 2. pin-strap output voltage settings v0 low open high low 0.6v 0.8v 1.0v v1 open 1.2v 1.5v 1.8v high 2.5v 3.3v 5.0v ZL6100
12 fn6876.1 september 8, 2009 example from figure 8: for v out = 1.33v, index1 = 4 x 1.33v = 5.32; from table 3, r1 = 16.2k index0 = (100 x 1.33v) ? (25 x 5) = 8; from table 3, r0 = 21.5k the output voltage can be determi ned from the r0 (index0) and r1 (index1) values using equation 2: smbus mode the output voltage may be set to any value between 0.6v and 5.0v using a pmbus command over the i 2 c/smbus interface. see application note an2033 for details. pola voltage trim mode the output voltage mapping can be changed to match the voltage setting equations for pola and dosa standard modules. the standard method for adjusting the output voltage for a pola module is defined by equation 3: the resistor, r set , is external to the pola module (see figure 9). to stay compatible with this existing method for adjusting the output voltage, the module manufacturer should add a 10k resistor on the module as shown in figure 10. now, the same r set used for an analog pola module will provide the same output voltage when using a digital pola module based on the ZL6100. the pola mode is activated through pin-strap by connecting a 110k resistor on v0 to sgnd. the v1 pin is then used to adjust the output voltage as shown in table 4 . table 3. resistors fo r setting output voltage index r0 or r1 (k ) index r0 or r1 (k ) 0101334.8 1111438.3 2 12.1 15 42.2 3 13.3 16 46.4 4 14.7 17 51.1 5 16.2 18 56.2 6 17.8 19 61.9 7 19.6 20 68.1 8 21.5 21 75 9 23.7 22 82.5 10 26.1 23 90.9 11 28.7 24 100 12 31.6 v out index 025 xindex 1 () + 100 -------------------------------------------------------- = (eq. 2) figure 8. output voltage resistor setting example v in v out 1.33v gh gl zl sw v0 r0 21.5 ko v1 r1 16.2 k o r set 10 k 0.69 v v out 0.69 v ? --------------------------------- - 1.43 k ? = (eq. 3) figure 9. output voltage setting on pola module - + 1.43ko r set 0.69v 10ko v out pola module figure 10. r set on a pola module ZL6100 10ko pola module r set v1 v0 110ko ZL6100
13 fn6876.1 september 8, 2009 dosa voltage trim mode on a dosa module, the v out setting follows equation 4: to maintain dosa compatibility, the same scheme is used as with a pola module except the 10k resistor is replaced with a 8.66k resistor as shown in figure 11. the dosa mode v out settings are listed in table 5. start-up procedure the ZL6100 follows a specific internal start-up procedure after power is applied to the vdd pin. table 6 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the en pin. the device requires approximately 5ms to 10ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mode pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requires approximat ely 2ms before its output voltage may be allowed to start its ramp-up pr ocess. if a soft-start delay period less than 2ms has been configured (using dly pins or pmbus commands), the device will default to a 2ms delay period. if a delay period greate r than 2ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft-start ramp time that has been set using the ss pin. it should be noted that if the en pin is tied to vdd, the device will still require approx 5ms to 10ms before the output can begin its ramp-up as described in table 6. table 4. pola mode v out settings (r0 = 110k, r1 = r set + 10k) v out (v) r set in series with 10k resistor (k ) v out (v) r set in series with 10k resistor (k ) 0.700 162 0.991 21.5 0.752 110 1.000 19.6 0.758 100 1.100 16.2 0.765 90.9 1.158 13.3 0.772 82.5 1.200 12. 0.790 75.0 1.250 9.09 0.800 56.2 1.500 7.50 0.821 51.1 1.669 5.6 0.834 46.4 1.800 4.64 0.848 42.2 2.295 2.87 0.880 34.8 2.506 2.37 0.899 31.6 3.300 1.21 0.919 28.7 5.000 0.162 0.965 23.7 r set 6900 v out 0.69 v ? --------------------------------- - = (eq. 4) figure 11. r set on a dosa module ZL6100 8.66 k dosa module r set v1 v0 110 k table 5. dosa mose v out settings (r0 = 110k, r1 = r set + 8.66k) v out (v) r set in series with 8.66k resistor (k ) v out (v) r set in series with 8.66k resistor (k ) 0.700 162 0.991 22.6 0.752 113 1.000 21.0 0.758 100 1.100 17.8 0.765 90.9 1.158 14.7 0.772 82.5 1.200 13.3 0.790 75.0 1.250 10.5 0.800 57.6 1.500 8.87 0.821 52.3 1.669 6.98 0.834 47.5 1.800 6.04 0.848 43.2 2.295 4.32 0.880 36.5 2.506 3.74 0.899 33.2 3.300 2.61 0.919 30.1 5.000 1.50 0.965v 25.5 ZL6100
14 fn6876.1 september 8, 2009 soft-start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, t he designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the ZL6100 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay period is set using the dly (0, 1) pins. precise ramp delay timing reduces the delay time variations but is only available when the appropriate bit in the misc_config register has been set. please refer to application note an2033 for details. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft start delay and ramp times can be set to standard values according to tables 7 and 8 respectively. note: when the device is set to 0ms or 1ms delay, it will begin its ramp up after the internal circuitry has initialized (~2ms). note: when the device is set to 0ms ramp, it will attempt to ramp as fast as the external load capacitance and loop settings will allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. if the desired soft start delay and ramp times are not one of the values listed in tables 7 and 8, the times can be set to a custom value by connecting a re sistor from the dly0 or ss pin to sgnd using the appropriate resistor value from table 9. the value of this resi stor is measured upon start-up or restore and will not change if the resistor is varied after power has been applied to the ZL6100. see figure 12 for typical connections using resistors. table 6. ZL6100 start-up sequence step step name description time duration 1 power applied input voltage is applied to the ZL6100?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for values stored in its internal memory. this step is also performed after a restore command. approx 5ms to 10ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads values configured by the multi- mode pins. 4 device ready the device is ready to accept an enable signal. - 5 pre-ramp delay the device require s approximately 2ms following an enable signal and prior to ramping its output. additional pre-ramp delay may be configured using the delay pins. approximately 2ms table 7. soft-start delay settings dly0 low (ms) open (ms) high (ms) low 012 dly1 open 51020 high 50 100 200 table 8. soft-start ramp settings ss ramp time (ms) low 0 open 5 high 10 table 9. dly and ss resistor settings dly or ss (ms) r dly or r ss (k ) dly or ss (ms) r dly or r ss (k ) 0 10 110 28.7 10 11 120 31.6 20 12.1 130 34.8 30 13.3 140 38.3 40 14.7 150 42.2 50 16.2 160 46.4 60 17.8 170 51.1 70 19.6 180 56.2 80 21.5 190 61.9 90 23.7 200 68.1 100 26.1 ZL6100
15 fn6876.1 september 8, 2009 note: do not connect a resistor to the dly1 pin. this pin is not utilized for setting soft-start delay times. connecting an external resistor to this pin may cause conflicts with other device settings. the soft-start delay and ramp times can also be set to custom values via the i 2 c/smbus interface. when the ss delay time is set to 0ms, the device will begin its ramp-up after the internal circuitry has initialized (~2ms). when the soft-start ramp period is set to 0ms, the output will ramp-up as quickly as the output load capacitance and loop settings will allow. it is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. power-good the ZL6100 provides a power-good (pg) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. by default, the pg pin will assert if the output is within -10%/+15% of the target voltage. these limits and the polarity of the pin may be changed via the i 2 c/smbus interface. see application note an2033 for details. a pg delay period is defined as the time from when all conditions within the ZL6100 for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the ZL6100 pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 1ms, the pg delay will be set to 10ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/smbus as described in application note an2033. switching frequency and pll the ZL6100 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when using the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the sync pin is a unique pin that can perform multiple functions depending on how it is configured. the cfg pin is used to select the operating mode of the sync pin as shown in table 10. figure 13 illustrates the typical connections for each mode. configuration a: sync output when the sync pin is configur ed as an output (cfg pin is tied high), the device will run fr om its internal oscillator and will drive the resulting internal oscillator signal (preset to 400khz) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. configuration b: sync input when the sync pin is configured as an input (cfg pin is tied low), the device will auto matically check for a clock signal on the sync pin each time en is asserted. the ZL6100?s oscillator will then synchronize with the rising edge of the external clock. the incoming clock signal must be in the range of 200khz to 1.4mhz and must be stable when the enable pin is asserted. the clock signal must also exhibit the necessary performance requirements (see the ?electrical specifications? table beginning on page 3). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the ZL6100 will automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. configuration c: sync auto detect when the sync pin is configured in auto detect mode (cfg pin is left open), the device will automatically check for a clock signal on the sync pin after enable is asserted. if a clock signal is present, t he ZL6100?s oscillator will then synchronize the rising edge of the external clock. refer to ?configuration b: sync input?. if no incoming clock signal is present, the ZL6100 will configure the switching frequency according to the state of the sync pin as listed in table 15. in this mode, the ZL6100 will only read the sync pin connection during the start-up sequence. changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on if the user wishes to run the ZL6100 at a frequency not listed in table 11, the switching frequency can be set using an external resistor, r sync , connected between sync and sgnd using table 12. figure 12. dly and ss pin resistor connections ZL6100 ss r ss nc dly0 dly1 r dly table 10. sync pin function selection cfg pin sync pin function low sync is configured as an input open auto detect mode high sync is configured as an output f sw = 400khz ZL6100
16 fn6876.1 september 8, 2009 the switching frequency can also be set to any value between 200khz and 1. 33mhz using the i 2 c/smbus interface. the available fr equencies below 1.4mhz are defined by f sw = 8mhz/n, where the whole number n is 6 n 40. see application note an2033 for details. if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal ci rcuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). when multiple zilker labs devices are used together, connecting the sync pins together will force all devices to synchronize with each other. the cfg pin of one device must set its sync pin as an output and the remaining devices must have their sync pins set as auto detect. note : the switching frequency read back using the appropriate pmbus command will differ slightly from the selected values in table 12. the difference is due to hardware quantization. power train component selection the ZL6100 is a synchronous buck converter that uses external mosfets, inductor and capacitors to perform the power conversion process. t he proper selection of the external components is critical for optimized performance. to select the appropriate external components for the desired performance goals, th e power supply requirements listed in table 13 must be known. figure 13. sync pin configurations ZL6100 logic high cfg sync 200khz ? 1.33mhz ZL6100 cfg sync 200khz ? 1.4mhz ZL6100 n/c cfg sync a) sync = output b) sync = input ZL6100 n/c cfg sync ZL6100 r sync n/c cfg sync logic high logic low open c) sync = auto detect or or table 11. switching frequency selection sync pin frequency (hz) low 200k open 400k high 1m resistor see table 12 table 12. r sync resistor values r sync (k ) f sw (khz) r sync (k ) f sw (khz) 10 200 ? - 11 222 26.1 533 12.1 242 28.7 571 13.3 267 31.6 615 14.7 296 34.8 727 16.2 320 38.3 800 17.8 364 46.4 889 19.6 400 51.1 1000 21.5 421 56.2 1143 23.7 471 68.1 1333 ZL6100
17 fn6876.1 september 8, 2009 design goal trade-offs the design of the buck power stage requires several compromises among size, efficiency, and cost. the inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. size can be decreased by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through-hole inductors and capacitors; however these components are physically large. to start the design, select a switching frequency based on table 14. this frequency is a starting point and may be adjusted as the design progresses. inductor selection the output inductor selection process must include several trade-offs. a high inductance value will result in a low ripple current (i opp ), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient lo ad performance. therefore, a balance must be struck between output ripple and optimal load transient performance. a good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (i ostep ; see equation 5): now the output inductance can be calculated using equation 6, where v inm is the maximum input voltage: the average inductor current is equal to the maximum output current. the peak inductor current (i lpk ) is calculated using equation 7 where i out is the maximum output current. select an inductor rated for the average dc current with a peak current rating above the peak current computed . in overcurrent or short-circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some inductance to protect the load and the mosfets from damaging currents in this situation. once an inductor is selected , the dcr and core losses in the inductor are calculated. use the dcr specified in the inductor manufacturer?s datasheet. i lrms is given by where i out is the maximum output current. next, calculate the core loss of the selected inductor. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datasheet. add the core loss and the esr loss and compare the total loss to the maximum power dissipation recommendation in the inductor datasheet. output capacitor selection several trade-offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capacitors, also have relatively low capacitance values. many designs can use a combination of high capacitance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor cu rrent ramps up or down to the new steady state output current value. table 13. power supply requirements parameter range example value input voltage (v in ) 3.0v to 14.0v 12v output voltage (v out ) 0.6v to 5.0v 1.2v output current (i out ) 0a to ~25a 20a output voltage ripple (v orip ) < 3% of v out 1% of v out output load step (i ostep ) < io 50% of i o output load step rate - 10a/s output deviation due to loadstep - 50mv maximum pcb temp. +120c +85c desired efficiency - 85% other considerations various optimize for small size table 14. circuit design considerations frequency range efficiency circuit size 200khz to 400khz highest larger 400khz to 800khz moderate smaller 800khz to 1.4mhz lower smallest i opp i ostep = (eq. 5) (eq. 6) opp sw inm out out out i f v v v l ? ? ? ? ? ? ? ? ? = 1 (eq. 7) 2 opp out lpk i i i + = (eq. 8) 2 lrms ldcr i dcr p = (eq. 9) () 12 2 2 opp out lrms i i i + = ZL6100
18 fn6876.1 september 8, 2009 as a starting point, apportion on e-half of the output ripple voltage to the capacitor esr and the other half to capacitance, as shown in equations 10 and 11: use these values to make an in itial capacitor selection, using a single capacitor or severa l capacitors in parallel. after a capacitor has been selected, the resulting output voltage ripple can be calculated using equation 12: because each part of this equation was made to be less than or equal to half of the allo wed output ripple voltage, the v orip should be less than the desi red maximum output ripple. input capacitor it is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5v or 12v ?bulk? supply from an off-line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from equation 13: without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated above to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r diel ectric with low esr and 1.1x the maximum expected input voltage are recommended. bootstrap capacitor selection the high-side driver boost circuit ut ilizes an external schottky diode (d b ) and an external bootstrap capacitor (c b ) to supply sufficient gate drive for the high-side mosfet driver. d b should be a 20ma, 30v schottky diode or equivalent device and c b should be a 1f ceramic type rated for at least 6.3v. ql selection the bottom mosfet should be selected primarily based on the device?s r ds(on) and secondarily based on its gate charge. to choose ql, use equations 14, 15 and 16, and allow 2% to 5% of the output power to be dissipated in the r ds(on) of ql (lower output voltages and higher step-down ratios will be closer to 5%): calculate the rms current in ql as shown in equation 15: calculate the desired maximum r ds(on) as shown in equation 16: note that the r ds(on) given in the manufacturer?s datasheet is measured at +25c. the actual r ds(on) in the end-use application will be much higher. for example, a vishay si7114 mosfet with a junction temperature of +125c has an r ds(on) that is 1.4x higher than the value at +25c. select a candidate mosfet, and calculate the required gate drive current as shown in equation 17: keep in mind that the total allowed gate drive current for both qh and ql is 80ma. mosfets with lower r ds(on) tend to have higher gate charge requirements, whic h increases the current and resulting power required to turn them on and off. since the mosfet gate drive circuits are integrated in the ZL6100, this power is dissipated in the ZL6100 according to equation 18: qh selection in addition to the r ds(on) loss and gate charge loss, qh also has switching loss. the procedure to select qh is similar to the procedure for ql. first, assign 2% to 5% of the output power to be dissipated in the r ds(on) of qh using equation 18. as was done wit h ql, calculate the rms current as shown in equation 19: calculate a starting r ds(on) as follows, in this example using 5% select a mosfet and calculate the resulting gate drive current. verify that the combined gate drive current from ql and qh does not exceed 80ma. (eq. 10) 2 8 orip sw opp out v f i c = (eq. 11) opp orip i v esr = 2 (eq. 12) out sw opp opp orip c f i esr i v + = 8 (eq. 13) ) 1 ( d d i i out cinrms ? = (eq. 14) out out ql i v p = 05 . 0 (eq. 15) d i i lrms botrms ? = 1 (eq. 16) () 2 ) ( botrms ql on ds i p r = (eq. 17) g sw g q f i = (eq. 18) inm g sw ql v q f p = (eq. 19) d i i lrms toprms = out out qh i v p = 05 . 0 (eq. 20) (eq. 21) () 2 ) ( toprms qh on ds i p r = ZL6100
19 fn6876.1 september 8, 2009 next, calculate the switchin g time using equation 22: where q g is the gate charge of the selected qh and i gdr is the peak gate drive current available from the ZL6100. although the ZL6100 has a typical gate drive current of 3a, use the minimum guaranteed current of 2a for a conservative design. using the calculated switching time, calculate the switching power loss in qh using equation 23: the total power dissipated by qh is given by equation 24: mosfet thermal check once the power dissipations for qh and ql have been calculated, the mosfets junction temperature can be estimated. using the junction-to-case thermal resistance (r th ) given in the mosfet manufacturer?s datasheet and the expected maximum printed circuit board temperature, calculate the junction temperature as shown in equation 25: current sensing components once the current sense method has been selected (see ?current limit threshold selection? on page 19.?), the components are selected as follows. when using the inductor dcr sensing method, the user must also select an r/c network comprised of r1 and cl (see figure 14). for the voltage across c l to reflect the voltage across the dcr of the inductor, the time c onstant of the inductor must match the time constant of the rc network (see equation 26). for l , use the average of the nominal value and the minimum value. include the effects of tolerance, dc bias and switching frequency on the inductance when determining the minimum value of l . use the typical value for dcr. the value of r 1 should be as small as feasible and no greater than 5k for best signal-to-noise ratio. the designer should make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. in calculating the minimum value of r 1 , the average voltage across c l (which is the average i out . dcr product) is small and can be neglected. th erefore, the minimum value of r 1 may be approximated by using equation 27: where p r1pkg-max is the maximum power dissipation specification for the resistor package and p is the derating factor for the same paramete r (eg.: pr1pkg-max = 0.0625w for 0603 package, p = 50% @ +85c). once r 1-min has been calculated, solve for the maximum value of cl from using equation 28: and choose the next-lowest readily available value (eg.: for c l - max = 1.86f, c l = 1.5f is a good choice). then substitute the chosen value into the same equation and recalculate the value of r 1 . choose the 1% resistor standard value closest to this re-calculated value of r 1 . the error due to the mismatch of the two time constants is shown in equation 29: the value of r 2 should be simply five times that of r 1 : for the r ds(on) current sensing method, the external low side mosfet will act as the sensing element as indicated in figure 16. current limit threshold selection it is recommended that the user include a current limiting mechanism in their design to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the even t that the output is shorted to ground or an overload condit ion is imposed on the output. current limiting is accomplished by sensing the current through the circuit during a portion of t he duty cycle. output current sensing can be accomplished by measuring the voltage across a series resistive sensing element according to equation 31: (eq. 22) gdr g sw i q t = (eq. 23) sw out sw inm swtop f i t v p = (eq. 24) swtop qh qhtot p p p + = (eq. 25) () th q pcb j r p t t + = max figure 14. dcr current sensing v in v out gh gl isena ZL6100 isenb sw r1 cl r2 (eq. 26) dcr l c r l dcr l rc = ? = 1 / (eq. 27) ()() p pkg r out out in p v d v v d r ? ? ? + ? = ? ? ? max 1 2 2 max min 1 1 (eq. 28) dcr r l c l ? = ? ? min 1 max (eq. 29) % 100 1 1 ? ? ? ? ? ? ? ? ? ? ? ? = avg l l dcr c r (eq. 30) 1 2 5 r r ? = (eq. 31) sense lim lim r i v = ZL6100
20 fn6876.1 september 8, 2009 where: i lim is the desired maximum current that should flow in the circuit r sense is the resistance of the sensing element v lim is the voltage across the sensing element at the point the circuit should start limiting the output current. the ZL6100 supports ?lossless? current sensing by measuring the voltage across a resistive element that is already present in the circuit. this eliminates additional efficiency losses incurred by devices that must use an additional series resistance in the circuit. to set the current limit threshold, the user must first select a current sensing method. the ZL6100 incorporates two methods for current sensi ng, synchronous mosfet r ds(on) sensing and inductor dc resistance (dcr) sensing; figure 17 shows a simplified schematic for each method. the current sensing method can be selected using the ilim1 pin using table 15. the ilim0 pin must have a finite resistor connected to ground in order for table 15 to be valid. if no resistor is connected between ilim0 and ground, the default method is mosfet r ds(on) sensing. the current sensing method can be modified via the i 2 c/smbus interface. please refer to application note an2033 for details. in addition to selecting the current sensing method, the ZL6100 gives the power supply designer several choices for the fault response during over or undercurrent condition. the user can select the number of violations allowed before declaring fault, a blanking time and the action taken when a fault is detected. figure 15. current sensing methods v in v out gh gl isena ZL6100 isenb sw inductor dcr sensing (v out must be less than 4.0v) v in v out gh gl isena ZL6100 isenb sw mosfet r ds(on) sensing table 15. resistor settings for current sensing ilim0 pin (note 19) ilim1 pin current limiting configuration number of violations allowed (note 20) comments r ilim0 low ground-referenced, r ds(on) , sensing blanking time: 672ns 5 best for low duty cycle and low f sw r ilim0 open output-referenced, down-slope sensing (inductor dcr sensing) blanking time: 352ns 5 best for low duty cycle and high f sw r ilim0 high output-referenced, up-slope sensing (inductor dcr sensing) blanking time: 352ns 5 best for high duty cycle resistor depends on resistor value used; see table 16 notes: 19. 10k < r ilim0 < 100k 20. the number of violations allowed prior to issuing a fault response. ZL6100
21 fn6876.1 september 8, 2009 the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing). it is a configurable parameter. table 15 includes default parameters for the number of violations and the blanking time using pin-strap. once the sensing method has been selected, the user must select the voltage threshold (v lim ), the desired current limit threshold, and the resistance of the sensing element. the current limit threshold can be selected by simply connecting the ilim0 and ilim1 pins as shown in table 17. the ground-referenced sensing method is being used in this mode. the threshold voltage can also be selected in 5mv increments by connecting a resistor, r lim0 , between the ilim0 pin and ground according to table 18. this method is preferred if the user does not de sire to use or does not have access to the i 2 c/smbus interface and the desired threshold value is contained in table 18. the current limit threshold can also be set to a custom value via the i 2 c/smbus interface. please refer to application note an2033 for further details. table 16. resistor configured current sensing method selection r ilimi1 (k ) current sensing method number of violations allowed (note 21) 10 ground-referenced, r ds(on) , sensing best for low duty cycle and low f sw blanking time: 672ns 1 11 3 12.1 5 13.3 7 14.7 9 16.2 11 17.8 13 19.6 15 21.5 output-referenced, down-slope sensing (inductor dcr sensing) best for low duty cycle and high f sw blanking time: 352ns 1 23.7 3 26.1 5 28.7 7 31.6 9 34.8 11 38.3 13 42.2 15 46.4 output-referenced, up-slope sensing (inductor dcr sensing) best for high duty cycle blanking time: 352ns 1 51.1 3 56.2 5 61.9 7 68.1 9 75 11 82.5 13 90.9 15 note: 21. the number of violations allowed prior to issuing a fault response table 17. current limit threshold voltage pin-strap settings ilim0 low (mv) open (mv) high (mv) low 20 30 40 ilim1 open 50 60 70 high 80 90 100 table 18. current limit threshold voltage resistor settings r lim0 (k ) v lim for rds (mv) v lim for dcr (mv) 10 0 0 11 5 2.5 12.1 10 5 13.3 15 7.5 14.7 20 10 16.2 25 12.5 17.8 30 15 19.6 35 17.5 21.5 40 20 23.7 45 22.5 26.1 50 25 28.7 55 27.5 31.6 60 30 34.8 65 32.5 38.3 70 35 46.4 80 40 51.1 85 42.5 56.2 9 45 68.1 100 50 82.5 110 55 100 120 60 ZL6100
22 fn6876.1 september 8, 2009 loop compensation the ZL6100 operates as a voltage-mode synchronous buck controller with a fixed fre quency pwm scheme. although the ZL6100 uses a digital control loop, it operates much like a traditional analog pwm controller. figure 16 is a simplified block diagram of the ZL6100 control loop, which differs from an analog control loop only by the constants in the pwm and compensation blocks. as in the analog controller case, the compensation block compares the output voltage to the desired voltage reference and compensation zeroes are added to keep the loop stable. the resulting integrated error signal is used to drive the pwm logic, converting the error signal to a duty cycle to drive the external mosfets. in the ZL6100, the compensation zeros are set by configuring the fc0 and fc1 pins or via the i 2 c/smbus interface once the user has calculated the requ ired settings. this method eliminates the inaccuracies due to the component tolerances associated with using external resistors and capacitors required with traditional analog controllers. utilizing the loop compensation settings shown in table 19 will yield a conservative crossover frequency at a fixed fraction of the switching frequency (f sw /20) and 60 of phase margin. step 1: using equation 32, calculate the resonant frequency of the lc filter, fn . step 2: based on table 19 determine the fc0 settings. step 3: calculate the esr zero frequency (f zesr ) using equation 33. step 4: based on table 19 determine the fc1 setting. adaptive compensation loop compensation can be a time-consuming process, forcing the designer to accommodate design trade-offs related to performance and stability across a wide range of operating conditions. the ZL6100 offers an adaptive compensation mode that enables the user to increase the stability over a wider range of loading conditions by automatically adapting the loop compensation coefficients for changes in load current. setting the loop compensation coefficients through the i 2 c/smbus interface allows for a second set of coefficients to be stored in the device in order to utilize adaptive loop compensation. this algorithm uses the two sets of compensation coefficients to determine optimal compensation settings as the output load changes. please refer to application note an2033 for further details on pmbus commands. figure 16. control loop block diagram d 1-d v in v out l c dpwm r c compensation r o (eq. 32) c l f n = 2 1 (eq. 33) crc f zesr 2 1 = table 19. pin-strap settings for loop compensation fc0 range fc0 pin fc1 range fc1 pin f sw /60 < f n < f sw /30 high f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low f sw /120 < f n < f sw /60 open f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low f sw /240 < f n < f sw /120 low f zesr > f sw /10 high f sw /10 > f zesr > f sw /30 open reserved low ZL6100
23 fn6876.1 september 8, 2009 non-linear response (nlr) settings the ZL6100 incorporates a non-linear response (nlr) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. this scheme results in a higher equivalent loop bandwidth than what is possible using a traditional linear loop. when a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the nlr circuitry will force a positive correction signal that will turn on the upper mosfet and quickly force the output to increase. conversely, a negative load step (i.e. removing a large load current) will cause the nlr circuitry to force a negative correction signal that will turn on the lower mosfet and quickly force the output to decrease. the ZL6100 has been pre-configured with appropriate nlr settings that correspond to the loop compensation settings in table 19. please refer to application note an2032 for more details regarding nlr settings. efficiency optimized driver dead-time control the ZL6100 utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom fets. in a synchronous buck converter, the mosfet drive circuitry must be designed such that the top and bottom mosfets are never in the conducting state at the same time. potentially damaging currents flow in the circuit if both top and bottom mosfets are simultaneously on for periods of time exceeding a few nanoseconds. conversely, long periods of time in which both mosfets are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. it is therefore advantageous to minimize this dead-time to provide optimum circuit efficiency. in the first order model of a buck converter, the duty cycle is determined by equation 34: however, non-idealities exist that cause the real duty cycle to extend beyond the ideal. dead-time is one of those non-idealities that can be manipulated to improve efficiency. the ZL6100 has an internal algor ithm that constantly adjusts dead-time non-overlap to minimize duty cycle, thus maximizing efficiency. this circuit will null out dead-time differences due to component variation, temper ature, and loading effects. this algorithm is independent of application circuit parameters such as mosfet type, gate driver delays, rise and fall times and circuit layout. in addition, it does not require drive or mosfet voltage or curren t waveform measurements. adaptive diode emulation most power converters use synchronous rectification to optimize efficiency over a wide range of input and output conditions. however, at light loads the synchronous mosfet will typically sink cu rrent and introduce additional energy losses associated with higher peak inductor currents, resulting in reduced efficiency. adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. diode emulation is available to single-phase devices. note: the overall bandwidth of the device may be reduced when in diode emulation mode. it is recommended that diode emulation is disabled prior to applying significant load steps. adaptive frequency control since switching losse s contribute to the efficiency of the power converter, reducing the switching frequency will reduce the switching losses and increase efficiency. the ZL6100 includes adaptive frequency control mode, which effectively reduces the observed switching frequency as the load decreases. adaptive frequency mode is enabled by setting bit 0 of misc_config to 1 and is only available while the device is operating within adaptive di ode emulation mode. as the load current is decreased, diode emulation mode decreases the gl on-time to prevent negative inductor current from flowing. as the load is decreased further, the gh pulse width will begin to decrease while maintaining the programmed frequency, f prog (set by the freq_switch command). once the gh pulse width (d) reaches 50% of the nominal duty cycle, d nom (determined by v in and v out ), the switching frequency will start to decrease according to equations 35, 36 and 37: if: in out v v d (eq. 34) figure 17. adaptive frequency switching frequency duty cycle f min f prog f sw (d) d d nom 2 0 switching frequency (f sw ) duty cycle (eq. 35) 2 nom d d < ZL6100
24 fn6876.1 september 8, 2009 then: otherwise: refer to figure 17. due to quantizing effects inside the ic, the ZL6100 will decrease its frequency in steps between f sw and f min . the quantity and magnitude of the steps will depend on the difference between f sw and f min as well as the frequency range. it should be noted that adapt ive frequency mode is not available for current sharing groups and is not allowed when the device is placed in auto-detect mode and a clock source is present on the sync pin, or if the device is outputting a clock signal on its sync pin. power management functional description input undervoltage lockout the input undervoltage lockout (uvlo) prevents the ZL6100 from operating when the input fa lls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85v and 16v using the uvlo pin. the simplest implementation is to connect the uvlo pin as shown in table 20. if the uvlo pin is left unconnected, the uvlo threshold will default to 4.5v. i f the desired uvlo threshold is not one of the listed choices, the user can confi gure a threshold between 2.85v and 16v by connecting a resistor between the uvlo pin and sgnd by selecting the appropriate resistor from table 21. the uvlo voltage can also be set to any value between 2.85v and 16v via the i 2 c/smbus interface. once an input undervoltage fault condition occurs, the device can respond in a number of ways as shown in steps 1, 2 and 3. 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdown until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the device. the device will continuously check for the presence of the fault cond ition. if the fault condition is no longer present, the ZL6100 will be re-enabled. please refer to application note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. output overvoltage protection the ZL6100 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (the default setting). if the vsen voltage e xceeds this threshold, the pg pin will de-assert and the device can then respond in a number of ways as shown in steps 1 and 2. 1. initiate an immediate shutdown until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosf et remains on until the device attempts a restart. the default response from an overvoltage fault is to immediately shut down. the device will continuously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. for continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown. please refer to application note an2033 for details on how to select specific overvoltage fault response options via i 2 c/smbus. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre- bias condition exists at the table 20. uvlo threshold settings pin setting uvlo threshold (v) low 3 open 4.5 high 10.8 table 21. uvlo resistor values r uvlo (k ) uvlo (v) r uvlo (k ) uvlo (v) 17.8 2.85 46.4 7.42 19.6 3.14 51.1 8.18 21.5 3.44 56.2 8.99 23.7 3.79 61.9 9.9 26.1 4.18 68.1 10.9 28.7 4.59 75 12 31.6 5.06 82.5 13.2 34.8 5.57 90.9 14.54 38.3 6.13 100 16 42.2 6.75 (eq. 36) min nom min sw f d d f f + ? ? ? ? ? ? ? ) ( 2 f sw (d) = f sw d () f prog = (eq. 37) ZL6100
25 fn6876.1 september 8, 2009 output. the ZL6100 provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than the target voltage exists after the pre-configured delay perio d has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the ramp rate set by the ss pin. the actual time the output will ta ke to ramp from the pre-bias voltage to the target voltage will vary depending on the pre- bias voltage but the total time elapsed from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time. see figure 18. if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre-bias voltage. once the pre-configured soft-start ramp period has expired, the pg pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit). the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage. if a pre-bias voltage higher th an the overvoltage limit exists, the device will not initiate a turn-on sequence and will declare an overvoltage fault condition to exist. in this case, the device will respond based on the output overvoltage fault response method that has been selected. see ?output overvoltage protection? on page 24. for response options due to an overvoltage condition. pre-bias protection is not offered for current sharing groups that also have tracking enabled. output overcurrent protection the ZL6100 can protect the pow er supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. once t he current limit threshold has been selected (see section ?current limit threshold selection? on page 19), the user may determine the desired course of action in response to the fault condition. the following steps 1 through 5 overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an over current fault is an immediate shutdown of the device. the device will continuously check for the presence of the f ault condition, and if the fault condition no longer exists the device will be re-enabled. please refer to application note an2033 for details on how to select specific overcurr ent fault response options via i 2 c/smbus. thermal overload protection the ZL6100 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as shown in steps 1 through 5: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. figure 18. output responses to pre-bias voltages ZL6100
26 fn6876.1 september 8, 2009 4. continue operating through the fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the device to restart, the device will wait the preset delay period (if configured to do so) and will then check the device tem perature. if the temperature has dropped below a threshold that is approximately +15c lower than the selected temperature fault limit, the device will attempt to re-start. if the temperature still exceeds the fault limit the device will wait the preset delay period and retry again. the default response from a temperature fault is an immediate shutdown of the device. the device will continuously check for the faul t condition, and once the fault has cleared the ZL6100 will be re-enabled. please refer to application note an2033 for details on how to select specific temperature fault response options via i 2 c/smbus. voltage tracking numerous high performance systems place stringent demands on the order in whic h the power supply voltages are turned on. this is particular ly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most cases, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage between multiple power supplies during the power-up and power down sequence. the ZL6100 integrates a lossless tracking scheme that allows its output to track a voltage that is applied to the vtrk pin with no external components required. the vtrk pin is an analog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. the ZL6100 offers two modes of tracking: 1. coincident . this mode configures the ZL6100 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. 2. ratiometric . this mode configures the ZL6100 to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio. figure 19 illustrates the typical connection and the two tracking modes. the master ZL6100 device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 10ms must be configured into the master device using the dly(0,1) pins, and the user may also configure a specific ramp rate using the ss pin. any device that is configured for tracking mode will ignore its soft-start delay and ramp time settings (ss and dly(0,1) pins) and its output will take on the turn-on/turn-off characteristics of the reference voltage present at the vtrk pin. all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking is configured via the i 2 c/smbus interface by using the track_config pmbus comm and. please refer to application note an2033 for more information on configuring tracking mode using pmbus. voltage margining the ZL6100 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set by driving the mgn pin or through the i 2 c/smbus interface. the mgn pin is a tri-le vel input that is continuously monitored and can be driven directly by a processor i/o pin or other logic-level output. the ZL6100?s output will be forced higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limits can be modified through the i 2 c/smbus interface to as high as v nom + 10% or figure 19. tracking modes v out v out time coincident ratiometric v trk v in v out q1 q2 l1 c1 gh gl sw ZL6100 vtrk v trk v out v out time v trk ZL6100
27 fn6876.1 september 8, 2009 as low as 0v, where v nom is the nominal output voltage set point determined by the v0 and v1 pins. a safety feature prevents the user from confi guring the output voltage to exceed v nom + 10% under any conditions. the margin limits and the mgn command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nominal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an2033 for detailed instructions on modifying t he margining configurations. i 2 c/smbus commu nications the ZL6100 provides an i 2 c/smbus digital interface that enables the user to configur e all aspects of the device operation as well as monitor the input and output parameters. the ZL6100 can be used with any standard 2- wire i 2 c host device. in addition, the device is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors are required on the i 2 c/smbus as specified in the smbus 2. 0 specification. the ZL6100 accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin is tied to sgnd. i 2 c/smbus device address selection when communicating with multiple smbus devices using the i 2 c/smbus interface, each devic e must have its own unique address so the host can dist inguish between the devices. the device address can be set according to the pin-strap options listed in table 22. address values are right-justified. if additional device addresses are required, a resistor can be connected to the sa0 pin according to table 23 to provide up to 25 unique device addresses. in this case, the sa1 pin should be tied to sgnd. if more than 25 unique device addresses are required or if other smbus address values are desired, both the sa0 and sa1 pins can be configured with a resistor to sgnd according to equation 38 and table 24. using this method, the user can theoretically configure up to 625 unique smbus addresses, however the smbus is inherently limited to 128 devices so attempting to configure an address higher than 128 (0x80) will cause the device address to repeat (i.e, attempting to configure a device address of 129 (0x81) would result in a device address of 1). therefore, the user should us e index values 0-4 on the sa1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. table 22. smbus device address selection sa0 low open high low 0x20 0x21 0x22 sa1 open 0x23 0x24 0x25 high 0x26 0x27 reserved table 23. smbus address values r sa (k ) smbus address r sa (k ) smbus address 10 0x00 34.8 0x0d 11 0x01 38.3 0x0e 12.1 0x02 42.2 0x0f 13.3 0x03 46.4 0x10 14.7 0x04 51.1 0x11 16.2 0x05 56.2 0x12 17.8 0x06 61.9 0x13 19.6 0x07 68.1 0x14 21.5 0x08750x15 26.1 0x0a 90.9 0x17 28.7 0x0b 100 0x18 31.6 0x0c table 24. smbus address index values r sa (k ) sa0 or sa1 index r sa (k ) sa0 or sa1 index 10 0 34.8 13 11 1 38.3 14 12.1 2 42.2 15 13.3 3 46.4 16 14.7 4 51.1 17 16.2 5 56.2 18 17.8 6 61.9 19 19.6 7 68.1 20 21.5 8 75 21 23.7 9 82.5 22 26.1 10 90.9 23 28.7 11 100 24 31.6 12 smbusaddress 25 sa1 ( ? index ) sa0 index ) in decimal () ( + = (eq. 38) ZL6100
28 fn6876.1 september 8, 2009 to determine the sa0 and sa1 resistor values given an smbus address (in decimal), follow the indicated steps to calculate an index value and then use table to select the resistor that corresponds to the calculated index value as shown in steps 1 through 5: 1. calculate sa1 index: sa1 index = address (in decimal) 25 2. round the result down to the nearest whole number. 3. select the value of r1 from table using the sa1 index rounded value from step 2. 4. calculate sa0 index: sa0 index = address ? (25 x sa1 index) 5. select the value of r0 from table 24 using the sa0 index value from step 4. digital-dc bus the digital-dc (ddc) communications bus is used to communicate between zilker labs digital-dc devices. this dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise time as follows: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to vr or to an external 3.3v or 5v supply as long as this voltage is present prior to or during device power-up. as rules of thumb, each device connect ed to the ddc bus presents approx 10pf of capacitive loading, and each inch of fr4 pcb trace introduces approx 2pf. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8v at the device monitoring point) given the pull-up voltage (5v if tied to vr) and the pull-down current capability of the zl61 00 (nominally 4ma). phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not al l devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronized to the same swit ching clock. the cfg pin is used to set the configuration of the sync pin for each device as described in section ?switching frequency and pll? on page 15. selecting the phase offset for the device is accomplished by selecting a device address according to equation 40: for example: ? a device address of 0x00 or 0x20 would configure no phase offset ? a device address of 0x01 or 0x21 would configure 45 of phase offset ? a device address of 0x02 or 0x22 would configure 90 of phase offset the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/smbus interface. refer to application note an2033 for further details. output sequencing a group of digital-dc devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface or by using zilker labs patented autonomous sequencing mode. autonomous sequencing mode configures sequencing by using events transmitted between devices over the ddc bus. this mode is not available on current sharing rails. the sequencing order is determined using each device?s smbus address. using autonomous sequencing mode (configured using the cfg pin), the devices must be assigned sequential smbus addresses with no missing addresses in the chain. this mode will also constrain each device to have a phase offset according to its smbus address as described in section ?phase spreading? on page 28?. the sequencing group will turn on in order starting with the device with the lowest smbus address and will continue through to turn on each device in the address chain until all devices connected have been turned on. when turning off, the device with the highest smbus address will turn off first followed in reverse order by the other devices in the group. sequencing is configured by co nnecting a resistor from the cfg pin to ground as described in table 25. the cfg pin is also used to set the configurat ion of the sync pin as well as to determine the sequencing method and order. please refer rise time r pu c load ? 1 s = (eq. 39) phase offset device address x 45 = (eq. 40) ZL6100
29 fn6876.1 september 8, 2009 to ?switching frequency and pll? on page 15? for more details on the operating parameters of the sync pin. multiple device sequencing may also be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. this method places fewer restrictions on smbus address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its smbus device address. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven low to initiate a sequenced turnoff of the group. refer to application note an2033 for details on sequencing via the i 2 c/smbus interface. fault spreading digital dc devices can be configured to broadcast a fault event over the ddc bus to the other devices in the group. when a non-destructive fault occurs and the device is configured to shut down on a faul t, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together if configured to do so, and will attempt to re-start in their prescribed order if configured to do so. temperature monitoring using the xtemp pin the ZL6100 supports measurement of an external device temperature using either a th ermal diode integrated in a processor, fpga or asic, or using a discrete diode-connected 2n3904 npn transistor. figure 20 illustrates the typical connections required. active current sharing paralleling multiple ZL6100 devices can be used to increase the output current capability of a single power rail. by connecting the ddc pins of each device together and configuring the devices as a current sharing rail, the units will share the current equally within a few percent. figure 21 illustrates a typical connection for three devices. the ZL6100 uses a low-bandwidth digital current sharing technique to balance the unequal device output loading by aligning the load lines of member devices to a reference device. figure 20. external temperature monitoring ZL6100 sgnd xtemp discrete npn 2n3904 ZL6100 sgnd xtemp embedded thermal diode p fpga dsp asic 100pf 100pf figure 21. current sharing group ZL6100 v out ZL6100 ZL6100 v in c out c in c out c in c out c in ddc ddc ddc 3.3v - 5v ZL6100
30 fn6876.1 september 8, 2009 droop resistance is used to add artificial resistance in the output voltage path to control t he slope of the load line curve, calibrating out the physical pa rasitic mismatches due to power train components and pcb layout. upon system start-up, the devi ce with the lowest member position as selected in ishare_config is defined as the reference device. the remaini ng devices are members. the reference device broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (vmember) to balance the current loading of each device in the system . figure 22 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by using equation 41: where r is the value of the droop resistance. the ishare_config command is used to configure the device for active current shar ing. the default setting is a stand-alone non-current sharing device. a current sharing rail can be part of a system sequencing group. for fault configuration, the curr ent share rail is configured in a quasi-redundant mode. in this mode, when a member device fails, the remaining members will continue to operate and attempt to maintain regulation. of the remaining devices, the device with the lowest member position will become the reference. if fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. up to eight (8) devices can be configured in a given current sharing rail. the maximum current for a current sharing rail is limited by the droop and nu mber of phases. refer to application note an2034 ?curr ent sharing with digital-dc? devices? for complete de tails on current sharing. phase adding/dropping the ZL6100 allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. in doing so, the power converter is optimized at a load current range that requires all phases to be oper ational. during periods of light loading, it may be beneficial to disable one or more phases in order to eliminate the curr ent drain and switching losses associated with those phases, resulting in higher efficiency. table 25. cfg pin configurations for sequencing r cfg (k ) sync pin congfiguration sequencing configuration 10 input seguencing is disabled 11 auto detect 12.1 output 14.7 input the ZL6100 is configured as the first device in a nested sequencing group. turn on order is based on the device smbus address. 16.2 auto detect 17.8 output 21.5 input the ZL6100 is configured as a last device in a nested sequencing group. turn on order is based on the device smbus address. 23.7 auto detect 26.1 output 31.6 input the ZL6100 is configured as the middle device in a nested sequencing group. turn on order is based on the device smbus address. 34.8 auto detect 38.3 output figure 22. active current sharing -r -r v reference v member i member i reference i out v out () member reference out member i i r v v ? + = (eq. 41) ZL6100
31 fn6876.1 september 8, 2009 the ZL6100 offers the ability to add and drop phases using a simple command in response to an observed load current change, enabling the system to continuously optimize overall efficiency across a wide load range. all phases in a current share rail are considered active prior to the current sharing rail ramp to power-good. phases can be dropped after power-good is reached. any member of the current shari ng rail can be dropped. if the reference device is dropped, the remaining active device with the lowest member position will become the new reference. additionally, any change to the number of members of a current sharing rail will pr ecipitate autonomous phase distribution within the rail where all active phases realign their phase position based on their order within the number of active members. if the members of a current s haring rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneous ly after the fault has cleared. monitoring via i 2 c/smbus a system controller c an monitor a wide vari ety of different ZL6100 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of pre-configured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: ? input voltage/output voltage ? output current ? internal junction temperature ? temperature of an external device ? switching frequency ? duty cycle the pmbus host should respond to salrt as follows: 1. zl device pulls salrt low 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl device that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application note an2033 for details on how to monitor specific parameters via the i 2 c/smbus interface. snapshot? parameter capture the ZL6100 offers a special mechanism that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. the snapshot feature enables the user to read the parameters listed in table 26 via a block read transfer through the smbus. this can be done during normal operation, although it shoul d be noted that reading the 22 bytes will occupy the smbus for some time. the snapshot_control command enables the user to store the snapshot parameters to flash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. table 27 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any fault threshold level is exceeded, prov ided that the specific fault?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the device?s v dd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requires between 700s to 1400s depending on whether the data is set up fo r a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. table 26. snapshot parameters byte description format 31:22 reserved linear 21:20 v in linear 19:18 v out v out linear 17:16 i out ,avg linear 15:14 i out ,peak linear 13:12 duty cycle linear 11:10 internal temp linear 9:8 external temp linear 7:6 f sw linear 5v out status byte 4i out status byte 3 input status byte 2 temp status byte 1 cml status byte 0 mfr specific status byte table 27. snapshot_control command data value description 1 copies current snapshot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot values to flash memory. only available when device is disabled. ZL6100
32 fn6876.1 september 8, 2009 in the event that the device experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). non-volatile memory and device security features the ZL6100 has internal non-volatile memory where user configurations are stored. in tegrated security measures ensure that the user can only restore the device to a level that has been made available to them. refer to ?start-up procedure? on page 13, for details on how the device loads stored values from internal memory during start-up. during the initialization process, the ZL6100 checks for stored values contained in its internal non-volatile memory. the ZL6100 offers two internal memory storage units that are accessible by the user as follows: 1. default store : a power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physical construction of the module. in this case, the module manufacturer would use the default store and would allo w the user to restore the device to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store : the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still pr otecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer woul d use the user store to achieve this goal. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/smbus interface. related tools and documentation the following application support documents and tools are available to help simplify your design. related documentation item description ZL6100eval1z evaluation board ? 40a single phase an2033 application note: digital-dc pmbus command set an2034 application note: digital-dc current sharing an2035 application note: digital- dc control loop compensation revision history the revision history provided is for informational purposes onl y and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 9/08/09 fn6876.1 initial release to web. ZL6100
33 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6876.1 september 8, 2009 quad flat no-lead plastic package (qfn) top view bottom view side view detail ?a? 0.10 c 2x 0.30 dia typ. 0.10 c 2x 8. 2 e a b seating plane 0.10 c 0.05 c 9. a1 a c a3 (datum a) d2/2 (datum b) see detail "a" bbb m c a b 0.05 m c nx b pin #1 id r0.20 see detail "a" (ne-1) x e 5. (nd-1) x e 2 n n-1 5. 9. 4. e2/2 e2 nx l d2 terminal tip datum a or b e/2 4. l l odd terminal/side even terminal/side 1 n d e k e e l36.6x6a 36 lead quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.80 0.85 0.90 - a1 0.00 0.02 0.05 - a3 0.20 ref - 0-122 k 0.20 min d 6.00 bsc - d2 4.00 4.10 4.20 - e 6.00 bsc - e2 4.00 4.10 4.20 - l 0.55 0.60 0.65 - b 0.18 0.25 0.30 4 e 0.50 bsc - n363 nd 9 5 ne 9 5 rev. 0 3/09 notes: 22. dimensioning and tolerancing conform to asme y14.5-1994. 23. all dimensions are in millimeters. is in degrees. 24. n is the number of terminals. 25. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.33mm from the terminal tip. if the terminal has optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 26. nd and ne refer to the number of terminals on each d and e side respectively. 27. max package warpage is 0.05m. 28. maximum allowable burrs is 0.076mm in all directions. 29. pin #1 id on top will be laser marked 30. bilateral coplaniarity zone appl ies to the exposed heat sink slug as well as the terminals. 31. this drawing conforms to jedec registered outline m0-229. ZL6100

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